The semiconductor industry has continually sought ways to produce memory devices with an increased number of memory cells per memory die. In non-volatile memory (e.g., NAND flash memory), one way to increase memory density is by using a vertical memory array, which is also referred to as a three-dimensional (3-D) memory array. One type of vertical memory array includes semiconductor pillars that extend through openings (e.g., holes) in tiers (e.g., layers, plates) of conductive material (e.g., word line plates, control gate plates), with dielectric materials at each junction of the semiconductor pillars and the conductive materials. Thus, multiple transistors can be formed along each pillar. Vertical memory array structures enable a greater number of transistors to be located in a unit of die area by building the array upwards (e.g., vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Vertical memory arrays and methods of forming them are described in, for example, U.S. Patent Application Publication No. 2007/0252201 of Kito et al.; Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15 (2007); Fukuzumi et al., “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory,” IEDM Technical Digest, pp. 449-52 (2007); and Endoh et al., “Novel Ultrahigh-Density Flash Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEEE Transactions on Electron Devices, vol. 50, no. 4, pp. 945-951 (April, 2003).
Conventional vertical memory arrays include an electrical connection between the conductive materials (e.g., word line plates) and access lines (e.g., word lines) so that memory cells in the 3-D array may be uniquely selected for writing, reading, or erasing operations. One method of forming an electrical connection includes forming a so-called “stair step” structure at an edge of the conductive materials. The stair step structure includes individual “steps” that define contact regions over which a vertical conductor is formed to provide electrical access to the respective conductive materials.
Further improvements and reductions in cost in the manufacturing of such structures, as well as alternative structures and methods for reducing an area covered by the stair step vertical memory arrays, are desired. In addition, improvements in the formation of structures including a higher number of memory cells and conductive tiers are desired.